As integrated circuit devices become more highly integrated, the space available for individual devices formed thereon is reduced. Accordingly, the sizes of patterns such as gates, bit lines, and metal lines formed on integrated circuits are generally reduced. Furthermore, space between these patterns is also generally reduced.
In particular, integrated circuit memory devices include a plurality of memory cells, and each memory cell is connected to other cells by conductive (metal) lines. The cells and conductive (metal) lines are connected to the substrate or other conductive layers by contact holes or via holes. The contact holes expose active regions of the substrate and the via holes expose the surface of other conductive layers. Patterned layers such as the gate electrodes should be isolated from the holes, and these patterned layers are generally arranged around the holes. Accordingly, the holes must be accurately placed in order to maintain electrical isolation with respect to the patterned layers such as the gate electrodes.
As the space between these patterned layers is reduced, however, the space available for forming the holes may also be reduced. Furthermore, there may be physical limits to the reductions which can be made to the size of the holes. Accordingly, the increased integration reduces the margin available in the placement of the holes. The margin available for the placement of the holes is also influenced by the process limitations of the steps for forming other adjacent patterns. For example, when a LOCOS field oxide layer is formed, the bird's beak phenomenon may reduce the active region. When a trench field oxide layer is formed, the inner wall of the trench may encroach into the active region also reducing the area available to the hole and further decreasing the margin for the formation of the hole.
FIG. 1 is a cross-sectional view of an integrated circuit device having a contact hole 16. The field oxide layer 12 is formed on the semiconductor substrate 10, and the gate electrode 14 is formed on an active region defined by the field oxide layer 12. Spacers 15 are formed along the sidewalls of the gate electrode 14. An insulating layer 20 is then formed on the surface of the substrate including the gate electrode 14 and the field oxide layer 12, and the contact hole 16 is formed therein to expose a portion of the active region of the substrate. The conductive layer 18 is formed on the insulating layer 20 thus filling the contact hole 16. The contact hole 16 is preferably formed over the active region between the gate electrode 14 and the field oxide film 12 so that neither the gate electrode 14 nor the field oxide film 12 is exposed.
While the contact hole 16 is shown centered between the gate electrode 14 and the field oxide layer 12 in FIG. 1, it may become more difficult to form the contact hole between these structures as the device integration increases. As the spaces become smaller, formation of the contact hole 16 may be limited by the physical characteristics of light and the ability to properly align the mask. Accordingly, the margin for error during the formation of the contact hole is reduced. As shown in FIGS. 2 and 3, misalignment of the contact hole photomask may cause the contact hole to expose either the gate electrode 14 or the field oxide layer 12.
As shown in FIG. 2, the misaligned contact hole 24 exposes a portion of the active region as well as a portion of the field region. This misalignment may also result in the formation of a well through the field oxide layer 12 thus exposing a portion of a field region of the substrate when etching the insulating film 20. In other words, a contact hole 24 may partially expose an active region of the substrate and a well in the field region of the substrate. Accordingly, when the contact hole 24 is filled with the conductive layer 18, the conductive layer 18 is brought into contact with the well. Leakage current may thus flow through the conductive layer 18 into the well area. The integrated circuit device may thus overload leading to a delay in the operation of the device or even a malfunction. If a capacitor is formed, the life of the capacitor may also be reduced.
In FIG. 3, a misaligned contact hole exposes a portion of the gate electrode 14. Accordingly, the conductive layer 18 filling the contact hole 25 may contact the gate electrode 14 thus short circuiting the device. The reliability of the integrated circuit device may thus be reduced.
As discussed above, margins for forming contact holes are reduced as device integration increases. For example, the extension of a gate or a field region may reduce the area available for a contact hole, thus reducing the process margins. The reduction of process margins in turn causes a reduction in the alignment margin for the photomask used to form the contact hole. Accordingly, alignment of the photomask may become more difficult. The contact holes for integrated circuit devices may thus be more difficult to form and the alignment thereof may also be more difficult.
Accordingly, there continues to exist a need in the art for improved contact hole structures and related methods.